1. Field of the Invention
The present invention relates to a semiconductor integrated circuit with built-in spark killer diodes suitable for output transistor protection.
2. Description of the Prior Art
For example, as a 3-phase motor driver, transistors (Tr1-Tr2, Tr3-Tr4, and Tr5-Tr6) which are connected in series between a direct current VCC and GND are connected in parallel as shown in FIG. 14. And, the 3-phase driver employs a circuit configuration wherein output terminals taken out from the Tr1-Tr2, Tr3-Tr4, and Tr5-Tr6 are connected to a motor M.
In such a case where the load is an inductive load, a forward/counter electromotive force occurs with a rotation/stop of the motor. Priorly, a protection diode is connected between the collector and emitter of series-connected transistors formed in an IC. And, diodes 12 are turned on when the output terminals become lower than the GND potential or higher than the VCC potential due to the counter electromotive force. Thereby, the electromotive force is released to a fixed potential to protect the inside of the IC including the series-connected transistors. In particular, when a large current of as much as several amperes is applied to the diodes 12, discrete components are used as the diodes 12.
Herein, users have a demand that the diodes 12 should also be formed in an IC for a reduction in the number of components of an apparatus. However, if diodes to which a large current of as much as several amperes is applied are integrated, a parasitic-current may flow due to a parasitic transistor effect that inevitably occurs in the integrated circuit. A parasitic current flows as a reactive current, and moreover, it contains a danger of latch up in the worst case.
In view of the above, as a structure to prevent a parasitic current, a structure as described in, for example, Japanese Unexamined Patent Publication No. Hei-6-100459 has been proposed.
As shown in FIG. 15, an N+-type buried layer 3 is provided between a Pxe2x88x92-type semiconductor substrate 1 and an Nxe2x88x92-type semiconductor substrate 2. In a manner surrounding this buried layer 3, a P+-type isolation region 4 is diffused from the surface of the semiconductor layer 2 to the semiconductor substrate 1, thereby forming one island 5. Then, on the buried layer 3, a P+-type buried layer 6 is formed in a partly overlapping manner. In a manner surrounding this P+-type buried layer 6, an N+-type derivative regions 7 from the semiconductor layer 2 surface to the N+-type buried layer 3 is formed. In this surrounded region, an N+-type diffusion region 8 is formed. Furthermore, in the region surrounded by the derivative region 7, formed is a P+-type derivative region 9 which surrounds the diffusion region 8 and reaches the P+-type buried layer 6 from the semiconductor layer 2. Furthermore, a cathode electrode 10 is provided in the diffusion region 8, and an anode electrode 11 is formed in the P+-type derivative region 9, and this anode electrode is electrically connected to the N+-type derivative region 7.
Namely, the P+-type derivative regions 9 and the P+-type buried layer 6 form an anode region, and an Nxe2x80x94type semiconductor region surrounded by the N+-type diffusion region 8 and derivative region 9 forms a cathode region, whereby a diode is constructed.
In such a diode element, created is a PNP-type parasitic transistor Tr2 which utilizes the N+-type buried layer 3 as a base, the P+-type buried layer 6 as an emitter, and the P-type semiconductor substrate 1 and the P+-type isolation layer 4 as a collector. However, since potential becomes the same between the base and emitter of this parasitic transistor Tr2 by a connection of the anode electrode, an ON-operation of the parasitic PNP transistor Tr2 can be prevented.
As described above, in the prior-art semiconductor integrated circuit device, if the load is an inductive load, a forward/counter electromotive force occurs with a rotation/stop of the motor, as shown in FIG. 14. Therefore, a protection diode is connected between the collector and emitter of the series-connected transistors formed in an IC. And, the diodes 12 are turned on when the output terminals become lower than the GND potential or higher than the VCC potential due to the counter electromotive force, whereby the electromotive force is released to a fixed potential. Thus, the inside of the IC including the series-connected transistors has been protected. In particular, when a large current of as much as several amperes was applied to the diodes 12, discrete components have been used as the diodes 12.
Moreover, for a demand that the diodes 12 should have also been formed in an IC for a reduction in the number of components of an apparatus, diodes to which a large current of as much as several amperes was applied have been integrated However, because of problems such that a parasitic current flowed due to a parasitic transistor effect that inevitably occurred in an integrated circuit and a reactive current flowed, a structure wherein the diodes were taken inside the IC was provided.
However, there is a case where although the diodes 12 could be taken inside the IC as mentioned above, the diodes 12 were off, that is, the cathode electrode 10 became higher in voltage than the anode electrode 11 as shown in FIG. 15. In this case, a withstand voltage to cope with a semiconductor element breakdown caused by a breakdown current at the PN-junction surface of a parasitic transistor TR1 is required. That is, the prior-art structure has a problem such that, since the width of the P+-type buried layer 6 as a base region of the parasitic transistor TR1 is narrow, a current amplification factor hfe cannot be easily controlled and a withstand voltage of the parasitic transistor TR1 cannot be secured.
Furthermore, as shown in FIG. 15, in the prior-art structure, potential becomes the same between the base and emitter so that the parasitic transistor TR2 can suppress an ON-operation, however, a leakage current flows via the substrate. Therefore, there exists a problem such that due to a leakage current of the parasitic transistor TR2, a desirable forward current cannot be obtained.
The present invention has been made in view of the above-described prior-art problems, and a semiconductor integrated circuit device of the present invention comprises: a semiconductor substrate of one conductivity type; at least one epitaxial layer(s) of the opposite conductivity type deposited on the surface of the substrate; a first opposite-conductivity-type buried layer formed between the substrate and a first epitaxial layer; a first one-conductivity-type buried layer which is formed between the substrate and the first epitaxial layer and is also formed in a manner overlapping with the first opposite-conductivity-type buried layer; a one-conductivity-type buried region which is connected to the first one-conductivity-type buried layer and is also connected to a first one-conductivity-type diffusion region formed in an uppermost epitaxial layer; an opposite-conductivity-type buried region which is connected to the first opposite-conductivity-type buried layer is also connected to a first opposite-conductivity-type diffusion region formed in the uppermost epitaxial layer; and a second opposite-conductivity-type diffusion region which is formed in the uppermost epitaxial layer in a manner surrounded by the first one-conductivity-type diffusion region, and is characterized in that a second one-conductivity-type diffusion region formed in the uppermost epitaxial layer is at least partly overlapped with the first one-conductivity-type diffusion region, and an anode electrode connects the first opposite-conductivity-type diffusion region and the second one-conductivity-type diffusion region.
Preferably, the semiconductor integrated circuit device of the present invention is characterized in that, with the second opposite-conductivity-type diffusion region, an opposite-conductivity-type well region is formed from the surface of the uppermost epitaxial layer in an overlapping manner.
Moreover, preferably, the semiconductor integrated circuit device of the present invention is characterized in that at least the upper surface of the first one-conductivity-type buried layer is located closer to the side of the second opposite-conductivity-type diffusion region than the upper surface of the first opposite-conductivity-type buried layer, and the first one-conductivity-type buried layer and the second opposite-conductivity-type diffusion region are formed with an interval in the depth direction.
First, in a diode element of a semiconductor integrated circuit device of the present invention, P-type first and second diffusion regions are formed so that both are partly overlapped with each other, and are characterized in that both are connected to an anode electrode at a part immediately over the second diffusion region. Thereby, parasitic resistance including the P-type second diffusion region can be increased. And, base potential of a parasitic PNP transistor can be securely made higher than the emitter potential. As a result, an operation of the PNP transistor when the diode element is on can be securely suppressed and a leakage current to a substrate can be greatly suppressed.
Second, a diode element of a semiconductor integrated circuit device of the present invention is characterized in that, similar to the first effect, parasitic resistance including the P-type second diffusion region can be increased. Thereby, collector potential of a parasitic NPN transistor can be securely made higher than the base potential. As a result, forward current of the diode element can be greatly increased by an operation of the parasitic NPN transistor.
Third, in a diode element of a semiconductor integrated circuit device of the present invention, by forming polysilicon with an impurity doped on the surface of the second epitaxial layer in place of the P-type second diffusion region, similar effects can be obtained. In other words, similar to the case of a P-type second diffusion region, by increasing parasitic resistance by polysilicon, the aforementioned first and second effects can be obtained.
Fourth, a diode element of a semiconductor integrated circuit device of the present invention is characterized in that, depending on usage application, etc., an N-type well region is formed in a second epitaxial layer so as to surround a cathode lead-out region. Thereby, owing to the N-type well region, the resistance value of an N-type region of a PN junction is lowered, whereby forward voltage (VBEF) is reduced. As a result, forward current characteristics (If) of the diode element can be greatly improved. And, the N-type well region can be formed at an arbitrary option based on a comparative consideration of the withstand voltage characteristics and forward current characteristics (If).